TSMC particulars N3 node evolution, outlines roadmap for 2nm-class nodes

The massive image: TSMC is making progress on its 3nm (N3) course of node plans, with N3E getting into quantity manufacturing later this 12 months. The corporate simply noticed its income slide for the primary time in 4 years, however it’s forging forward with vital R&D expenditures to make sure its 2nm-class nodes can be prepared earlier than Intel and others can catch up.

This week, TSMC showcased a number of the key options of its present and future course of node applied sciences on the 2023 North America Know-how Symposium in Santa Clara, California. The Taiwanese firm’s roadmap features a vary of latest silicon applied sciences for varied trade wants that stretches to 2026, and no fewer than 1,600 companions and clients are attending the occasion.

Presently, TSMC is utilizing 3nm tech (N3) in quantity manufacturing – most of it for Apple silicon – and an N3E node is on schedule to begin manufacturing within the second half of this 12 months. The advantages of N3 embody a velocity enchancment of 18 p.c on the identical energy as N5, with logic density approaching 1.6 occasions that of the older node. It is also much less advanced (and thus more cost effective) to make use of in comparison with N3 because it would not require EUV double patterning to realize the claimed density enhancements.

Beginning subsequent 12 months, TSMC is extending its 3nm portfolio with three new nodes: N3P, N3X, and N3AE. N3P is a refinement of N3E with the purpose of additional will increase in transistor density whereas providing 5 p.c higher efficiency on the identical energy or 5 to 10 p.c extra vitality effectivity on the identical clocks. And because it’s simply an optical shrink of N3E, designs based mostly on N3P can be forward-compatible, which means N3P will probably be a well-liked alternative amongst chip design corporations.

N3X is designed with high-performance computing in thoughts, so will probably be a lovely alternative for issues like CPUs, GPUs, and AI accelerators. This may afford clockspeeds which can be no less than 5 p.c larger in comparison with N3P at the price of larger leakage currents (and thus needing larger voltages for stability). TSMC says N3X will assist voltages round 1.2 volts, which means this node can be most helpful for server-grade {hardware} with beefy cooling techniques.

TSMC plans to have N3P in mass manufacturing someday within the second half of 2024, whereas N3X will not be prepared till 2025. Provide chain insiders declare Intel’s Celestial GPUs can be among the many first to make use of the latter node, however we’ll have to attend and see. As for N3AE, it is a node optimized for chips utilized in automotive functions that will even turn out to be accessible to carmakers in 2025.

One factor is for certain – N3 class nodes will speed up the event of chiplet-based architectures (AMD’s RDNA 3 involves thoughts) with compute dies made on the latest and best node and extra reminiscence and I/O dies made utilizing extra mature nodes with higher price effectivity and extra predictable yields.

The corporate additionally outlined a roadmap for 2nm (N2) course of nodes, which incorporate “nanosheet” (aka gate-all-around or GAAFET) transistors and permit for even higher efficiency, vitality effectivity, and elevated transistor densities for logic, SRAM, and analog circuits. One benefit over current FinFET transistors is a decrease leakage present, and one other is that channel width may be adjusted for both larger efficiency or decrease energy consumption.

In any other case, TSMC claims N2 will supply 10 to fifteen p.c extra efficiency on the identical energy as N3 or a 25 to twenty p.c energy discount on the identical clocks. The corporate can also be optimistic it could actually obtain blended chip densities (SRAM, logic, and analog) with N2 which can be greater than 15 p.c larger in comparison with N3E.

As for the way far alongside the event course of is, the brand new nanosheet transistors already meet 80 p.c of the goal efficiency specs, whereas the common yield of a 256Mb SRAM is at present hovering simply above 50 p.c. With high-volume manufacturing deliberate for 2025, the corporate has loads of time to enhance these figures.

The N2 household will increase someday in 2026 with N2P, which can add bottom energy supply. Similar to Intel’s PowerVia and Samsung’s BSPDN, the concept is to sandwich the transistors between the ability supply community and the sign community, enhancing transistor efficiency and decreasing energy consumption consequently.

It could not sound like a lot, however bottom energy supply networks are a number of the most necessary improvements within the semiconductor house in recent times. It modifications the best way energy is delivered to transistors on a chip in a means that improves energy effectivity and affords vital logic density enhancements. Based on Utilized Supplies estimates, bottom energy supply permits for logic cell space reductions of 20 to 30 p.c – the equal of two lithography generations value of enchancment.

N2P will not be prepared for quantity manufacturing till 2026 and TSMC has but to supply any figures on the way it compares to N2. It is a related story with N2X, the variant designed for high-performance computing the place voltages and clocks are pushed to the purpose of diminishing returns.

If something, Intel has a window of alternative to meet up with TSMC with the Intel 20A and 18A nodes, with the primary slated to enter quantity manufacturing in late 2024. Nevertheless, given Intel’s poor monitor file of delivering on schedule and the difficulties in securing bleeding-edge ASML EUV gear, we’re not anticipating any miracles.

Peter Johnson